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Table 40: Attribute Memor y Function
Function Mode
Standby
Read Byte Access CIS (8 bits)
Write Byte Access CIS (8 bits)
Invalid
Read Byte Access
Configuration (8 bits)
Write Byte Access
Configuration (8 bits)
Read Byte Access
Configuration CF+ (8 bits)
Read Word Access CIS (16
bits)
Write Word Access CIS (16
bits) Invalid
Read Word Access
Configuration (16 bits)
Write Word Access
Configuration (16 bits)
-REG
X
L
L
L
L
L
L
L
L
L
-CE2 (1)
H
H
H
H
H
H
L
L
L
L
-CE1 (1)
H
L
L
L
L
L
L
L
L
L
A10
X
L
L
L
L
X
L
L
L
L
A9
X
L
L
H
H
X
L
L
H
H
A0
X
L
L
L
L
L
X
X
X
X
-OE (1)
X
L
H
L
H
L
L
H
L
H
-WE (1)
X
H
L
H
L
H
H
L
H
L
D15 to D8
High-Z
High-Z
Don’t Care
High-Z
Don’t Care
High-Z
Not Valid
Don’t Care
Not Valid
Don’t Care
D7 to D0
High-Z
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
Even Byte
21
The – CE signal or both the – OE signal and the – WE signal must be de-asserted between consecutive cycle operations.
7.6 I/O Transfer Function
The I/O transfer to or from the Card can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the –
IOIS16 signal is asserted by the Card, otherwise it is de-asserted. When a 16 bit transfer is attempted, and the –
IOIS16 signal is not asserted, the system must generate a pair of 8 bit references to access the Word’s even and
odd Bytes. The Card permits both 8 and 16 bit accesses to all of its I/O addresses, so – IOIS16 is asserted for all
addresses (see Table 41).
Table 41: I/O Function
Function Code
Standby Mode
Byte Input Access
(8 bits)
Byte Output Access
(8 bits)
Word Input Access (16 bits)
Word Output Access (16 bits)
I/O Read Inhibit
I/O Write Inhibit
High Byte Input Only (8 bits)
High Byte Output Only (8 bits)
-REG
X
L
L
L
L
L
L
H
H
L
L
-CE2
H
H
H
H
H
L
L
X
X
L
L
-CE1
H
L
L
L
L
L
L
X
X
H
H
A0
X
L
H
L
H
L
L
X
X
X
X
-IORD
X
L
L
H
H
L
H
L
H
L
H
-IOWR
X
H
H
L
L
H
L
H
L
H
L
D15 to D8
High Z
High Z
High Z
Don’t Care
Don’t Care
Odd Byte
Odd Byte
Don’t Care
High Z
Odd Byte
Odd Byte
D7 to D0
High Z
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Even Byte
Don’t Care
High Z
High Z
Don’t Care
7.7 Common Memory Transfer Function
The Common Memory transfer to or from the Card permits both 8 or 16 bit access to all of the Common Memory
addresses (see Table 42).
Table 42: Common Memory Function
Function Code
Standby Mode
Byte Read Access
(8 bits)
Byte Write Access
(8 bits)
Word Read Access (16 bits)
Word Write Access (16 bits)
Odd Byte Read Only (8 bits)
Odd Byte Write Only (8 bits)
-REG
X
H
H
H
H
H
H
H
H
-CE2
H
H
H
H
H
L
L
L
L
-CE1
H
L
L
L
L
L
L
H
H
A0
X
L
H
L
H
X
X
X
X
-OE
X
L
L
H
H
L
H
L
H
-WE
X
H
H
L
L
H
L
H
L
D15 to D8
High Z
High Z
High Z
Don’t Care
Don’t Care
Odd Byte
Odd Byte
Odd Byte
Odd Byte
D7 to D0
High Z
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Even Byte
High Z
Don’t Care
7.8 True IDE Mode I/O Function
The Card can be configured in a True IDE Mode of operation. It is configured in this mode only when the – OE
signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol
and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. No Memory
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.20
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-320_data_sheet_CF-HxBO_Rev120.doc
Page 46 of 101
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